Eric Deal 1

Eric Deal
Bus. Phone: 512 200 2925

CNSV Member

IEEE Member

Consulting and IP for NAND flash, verilog design and architecture consulting, Verilog, SOC, FPGA

Eric Deal 2

10703 McFarlie Cove
Austin, CA 78750

Eric has 18 years of digital architecture and design experience in ASIC, SOC, and FPGA implementations. He is currently licensing BCH IP for NAND Flash applications and providing design consulting services through Cyclic Design (yes, he also loves cycling).

Eric is also collaborating with Zocalo Technologies, an EDA company providing tools to accelerate adoption of Assertion-Based Verification though the use of System Verilog Assertions.

Experienced with

  • BCH ECC and interfacing for NAND Flash
  • SOC bus architecture (AXI, custom)
  • Peripheral interfaces
  • Security (DES, AES, SHA)
  • ARM Processors (interfacing, assembly)
  • Verilog, C/C++, Perl, TCL, SQL, PHP, HTML, CSS

          Eric Deal 3