Rajagopal Maradana 1

Rajagopal Maradana, BSEE, MBA
FE ASIC LLC
raj.maradana@gmail.com
Bus. Phone: 669.234.9674

CNSV Member

IEEE Member

VLSI, SoC, ASIC physical design implementation, full chip integration, Timing/STA closure, Power closure, PPA optimization, Foundry Process Technologies, Packaging

2069 Owl Meadow St.
Folsom, CA 95630-6260
USA

ASIC/SOC Design Lead and Manager

  • Experienced in leading functional teams to execute RTL2GDS implementation for IPs, sub-system and SoC designs to tape out that includes foundry technology interface, process, PDK and IP selection
  • Strong organizational skills, strategic planning, team building skills focusing on efficiency and productivity
  • Held leadership roles at companies such as Intel, Micron Technology and Qualcomm
  • Solid foundation with an engineering degree in electrical and electronics and certifications in Artificial Intelligence, Risk Analysis, Semiconductor Packaging specialization and Leadership skills through business administration learning to support extensive career in engineering and management
  • Experienced in coordinating and leading Cadence and Synopsys tool flow methodology development and deployment, PPAS optimizations and signoff for different foundry process technology nodes

          Rajagopal Maradana 2