Teruo Utsumi
Bus. Phone: 408 370 9147
Mobile: 408.583.7412
CNSV Affiliate Member

FPGA & ASIC design, high-performance computing, supercomputers

102 Almond Hill Ct.
Los Gatos, CA 95032-1803

Teruo Utsumi has over 20 years of experience in computer hardware. His FPGA and ASIC design services include:

  • optimization of the hardware implementation of algorithms
  • chip design optimization at both high and micro-architectural levels
  • high performance computer architectures
  • staff training on FGPA resource utiliization to maximize speed and minimize chip utilization
  • analysis of the interactions between hardware and software
  • RAS (reliability, availability, and serviceabilility)
  • testing
  • design and design review

Teruo is a co-inventor of eleven patents.