IEEE Senior Member
Analog/RF/mmWave-TeraHertz IC design
Menlo Park, CA 94025
He has been responsible for the management and/or design of various semiconductor projects at the system level, transistor level and device level in CMOS and Bipolar technologies using various processes. Areas of experience include:
- Power Management
- Signal Conditioning
- Front end transceiver design
- Managing and setting up design centers at remote locations
- Providing targeted analog IP cores in diverse semiconductor processes
He has been employed at: National Semiconductor, Xicor, Georgia Tech, Unitech Research Inc., San Jose State University, NXP Semiconductors, Schneider Electric and AmpedRF Technology among others. He earned the B.S.E.E. from U.C. Davis (1989), the M.S.E.E. from San Jose State University (1994) and the Ph.D.E.E. (minor in mathematics) from the Georgia Institute of Technology (2005). His master’s and doctoral theses focused on analog IC design.
Professional service includes: Associate Editor of the IEEE Circuits and Systems Society Newsletter (’10-’17); Associate Editor of TELKOMNIKA Journal (’12-’17); reviewer for the journal “IEEE Transactions on Circuits and Systems II” (’08-’15); reviewer for IEEE ICECS; IEEE Santa Clara Valley (SCV) Circuits and Systems Society (Chair (’09), Vice-Chair (’08), Secretary (’07,’10), Treasurer (’08); IEEE SCV Solid State Circuits Society (Vice-Chair (’08), Treasurer (’07), Secretary/Webmaster (’06); IEEE SCV Communications Society (Secretary (’06); IEEE SCV Senior Member Advancement Chair (’06,’07,’08); IEEE SCV Treasurer (’09); elected 2010 Vice Chair of the IEEE Santa Clara Valley Section; contributing author of the IEEE Circuits and Systems Society Newsletter (’08-’17); Session Chair Circuits 1 Track: IEEE UGIM (’06); IEEE Circuits and Systems Society 2010 Region 1-7 (USA & Canada) Chapter of the Year Award. He is a Senior Member of the IEEE.