Semiconductors, consumer electronics, device debug, characterization, failure analysis, package, silicon.
Morgan Hill, CA 95037
I am an electrical engineer with expertise in electronic device failure analysis processes.
Background in product types including Integrated Circuit, CPU, SoC, and memory devices.
Experience with technologies including advanced semiconductor process nodes (14nm, 32nm, 22nm, …), CMOS, FinFET, and planar processes.
Package and silicon level analysis.
Skills and services:
- Fault Isolation (or Defect Localization)
- Electrical Characterization
- Root Cause Analysis
- Post-Silicon Debug
- FIB Circuit Editing
Tools and techniques:
- Photon Emission Microscopy (or IREM)
- Laser Voltage Probing
- Laser Assisted Device Alteration (for Soft Defect Localization)
- Scanning and Transmission Electron Microscopy
Member of EDFAS (Electronic Device Failure Analysis Society)