IEEE Meets the USPTO

Wednesday, Sep 13, 2017 - 5:00 pm to 8:00 pm          


This was a very special IEEE-CNSV-sponsored Open House at the Silicon Valley U.S. Patent & Trademark Office (USPTO) located in San Jose City Hall.  IEEE-CNSV members along with IEEE members and their guests learned about and got a tour of the resources offered at this new regional office, including the public search room (with facilities not available online), patent examiner meeting rooms, and the Patent Trial and Appeal Board (PTAB) hearing room.

Attendees met USPTO staff members, including Silicon Valley Office Director John Cabeca.  John and his team presented on intellectual property (IP) strategies and the risks of early disclosure, followed by a Q&A discussion.

Since IEEE provides a wealth of technical knowledge and experience, and since its publications represent a huge source of prior art and knowledge for inventors, attendees were encouraged to offer suggestions for ways in which IEEE locally can establish a closer relationship with this valuable facility that is in our backyard.  Indeed, the USPTO was very interested in engaging with IEEE.  Food and drink were provided at the event.

Follow-up questions may be directed to Julie Mason, Silicon Valley USPTO Regional Outreach Officer, at julie.mason@uspto.gov or 408.918.9775.

The Silicon Valley USPTO Office offered a warm welcome to IEEE-CNSV.

Patent Examiner Andrew Polay led a tour of the Silicon Valley USPTO Office.

CNSV Director Brian Berg provided opening remarks to the attendees.

West Coast Regional Director John Cabeca discussed the Silicon Valley USPTO facilities with the event guests.

Brian Berg and John Cabeca at the Silicon Valley USPTO Office.

speaker portrait

About the speaker, Brian A. Berg of Berg Software Design

Brian Berg has been a data storage technologist for over 30 years through his Berg Software Design consultancy. His current specialty is flash memory as used in consumer electronics and enterprise applications, particularly re: the Flash Translation Layer, embedded firmware and cell management. Brian works extensively with patents and intellectual property, including as a technical expert witness.

As Technical Chair of Flash Memory Summit, he organizes the annual Architecture session and vets candidates for the Lifetime Achievement Award. He has organized, chaired and spoken at over 100 technology conferences and industry events.

Brian has a long record as an IEEE officer and volunteer both in Silicon Valley and the western US. He has secured IEEE Milestones for the EEPROM/Flash Memory, the Apple Macintosh, SHAKEY the Robot and CDMA, and is a Core Member of the Computer History Museum.


About the speaker, John Cabeca of USPTO

As the Director of the Silicon Valley United States Patent and Trademark Office (USPTO), John Cabeca carries out the strategic direction of the Under Secretary of Commerce for Intellectual Property and Director of the USPTO, and is responsible for leading the USPTO’s west coast regional office in Silicon Valley. Focusing on the region and actively engaging with the community, Mr. Cabeca ensures the USPTO’s initiatives and programs are tailored to the region’s unique ecosystem of industries and stakeholders.

A veteran of the U.S. Patent and Trademark Office for over 26 years, Mr. Cabeca previously served as the Senior Advisor to the Under Secretary of Commerce for Intellectual Property and Director of the USPTO. In this role, he worked closely across the Agency’s leadership to implement the policies and priorities for the USPTO. He began his career at the USPTO as a patent examiner after graduating from Widener University with a bachelor’s degree in electrical engineering. Mr. Cabeca became a Supervisory Patent Examiner in 1997 and joined the Senior Executive Service in 2008 serving as a Patent Technology Center Director over the semiconductor and electrical systems technologies.

Mr. Cabeca has dedicated much of his career to the USPTO’s outreach and education programs focusing on small businesses, startups and entrepreneurs. Over the years, he served in the Office of Petitions, the Office of Patent Legal Administration, the Office of Governmental Affairs and the Office of the Under Secretary. In 2006, Mr. Cabeca was appointed a Department of Commerce Science and Technology Fellow and served on special assignment to the Executive Office of the President in the United States Trade Representative’s Office.  At USTR, he worked with multiple agencies on a variety of international intellectual property rights issues and played an integral role in the Free Trade Agreement negotiations with the Republic of Korea.


USPTO Silicon Valley Office
26 S Fourth St, San Jose, CA 95113
View Map & Directions