Conference: Flash Memory Summit 2014
Location: Santa Clara Convention Center, CA
The Flash Memory Summit is a 3-day conference: Tue-Thu, Aug. 5-7, plus a set of seminars on Mon, Aug. 6. Registration for the whole conference at earlybird prices, and for FREE admission to the Exhibition Area and a number of other sessions, is available herethrough Sun., Aug. 3. CNSV members can save $100 when registering for the full conference by using “IEEE” as their Priority Code.
CNSV will have a booth in the Exhibition Area. If you wish to be in this booth during part of the conference to promote both your consultancy and CNSV, contact Brian A. Berg.
This conference will provide attendees with practical information on the current state of flash memory and its applications. The program consists of tutorials, panel discussions, keynotes, paper sessions, workshops and special sessions.
The Wed., Aug. 6 tutorials cover these topics:
- Measuring Reliability in SSD Storage Systems
- Enabling Big Data Applications with Flash Memory
- Software-Defined Storage: Driven by Flash Technology
- Selecting the Right Enterprise SSD: Featuring the M.2 Form Factor.
Conference topics include Flash Memory-Based Architectures, Solid State Drives (SSDs), NVMe, PCIe, Next-Generation Controllers, Caching, Testing/Performance/Endurance, Virtualization, Error Correcting techniques and Enterprise applications.
Flash Memory is a type of nonvolatile memory that can be erased and rewritten in units called blocks. Flash is rugged, small, low-cost, low-power, and fast. It allows for compact systems with simple startup and low power consumption. It is ideal for consumer applications such as cellphones, digital cameras and music players, and is also useful in computers, communications systems and military/defense applications. It can replace hard disks for storage in applications where its higher cost is balanced by its smaller size, greater ruggedness, and lower power consumption.
In conjunction with the local IEEE PACE chapter, CNSV member Kiran Gunnam has created and is chairing a special tutorial titled LDPC Decoding: VLSI Architectures and Implementations that requires a separate registration here.
The entire conference is described in this Preview Program.
Location: Santa Clara Convention Center, CA
5001 Great America Parkway, Santa Clara, CA 95054
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